The present invention relates to a semiconductor device in which a defective portion of a semiconductor chip provided with an electronic circuit integrated in high density (hereinafter referred to as xe2x80x9cIC chipxe2x80x9d) can be easily analyzed by a photo-emission analyzing method, and particularly to a surface mount type semiconductor device in which a plurality of electrode bumps are provided in the form of a ball grid array (BGA) and which is packaged.
First, referring to the figures, the structure of a general BGA package type semiconductor device will be conceptually described.
FIG. 2 is a sectional side view of a thermal enhanced BGA package type semiconductor device, and FIG. 3 is a sectional side view of a plastic molded BGA package type semiconductor device.
A thermal enhanced BGA package (hereinafter referred to as xe2x80x9cE-BGAxe2x80x9d) type semiconductor device (hereinafter referred to simply as xe2x80x9cICxe2x80x9d) 20 shown in FIG. 2 comprises an IC chip 21 fixed to the back side of a metallic substrate 22 in an opening portion 24 formed at a central portion of a package substrate 23 laminated on the metallic substrate 22, with the side of power source, ground wiring and the like as well as a plurality of electrodes (not shown) of the IC chip 21 directed downward (hereinafter referred to xe2x80x9cface-downxe2x80x9d), wherein the electrodes are connected by wires 27 to electrode lands (not shown) provided on the package substrate 23, and the IC chip 21 is sealed with a sealing material 25. The package substrate 23 may be a monolayer substrate, but generally is of a multi-layer laminate substrate structure, and a plurality of electrode bumps 26 made of solder in ball shape are provided in a predetermined grid-like array on the back side of the lowest layer of the multi-layer substrate.
A plastic molded BGA package (hereinafter referred to as xe2x80x9cP-BGAxe2x80x9d) type IC 30 shown in FIG. 3 comprises an IC chip 31 fixed on a package substrate 32 provided with wirings such as electrode lands (not shown), with the side of power source, ground wirings and the like as well as a plurality of electrodes (not shown) of the IC chip 31 directed upward (hereinafter referred to as xe2x80x9cface-upxe2x80x9d), wherein the electrodes are connected by wires 33 to electrode lands (not shown) of the package substrate 32, and the IC chip 31 in such condition and the surface inclusive of the electrode lands of the package substrate 32 are sealed with a sealing resin 34. The package substrate 32 has the same structure as that of the package substrate 23, and a plurality of electrode bumps 35 are provided in a predetermined grid-like array on the back side of the lowest layer of the package substrate 32.
The E-BGA package type IC 20 (hereinafter referred to simply as xe2x80x9cIC 20xe2x80x9d) and the P-BGA package type IC 30 (hereinafter referred to simply as xe2x80x9cIC 30xe2x80x9d) are finally subjected to quality test in a factory, and then sold to the users such as an assembly maker. The user surface-mounts the IC 20 or IC 30 onto the user""s electronic circuit substrate by utilizing a substrate or taping.
As shown in FIG. 2, the IC 20 is surface mounted on the user""s electronic circuit substrate in the condition where the metallic substrate 22 is disposed on the upper side and the IC chip 21 is directed downward (face-down) so as to enhance heat radiation properties. As shown in FIG. 3, the IC 30 is surface mounted on the user""s electronic circuit substrate in the condition where the IC chip 31 is present on the upper side of the package substrate 32 (face-up).
After the IC 20 or IC 30 is mounted, or during the mounting, defective mounting or potential defects present in the IC 20 or IC 30 itself come to appear upon mounting, and the defective IC 20 or IC 30 is returned to the semiconductor maker side. On the semiconductor maker side, the reason of failure or defects in the IC 20 or IC 30 thus returned is analyzed. The analysis is usually carried out by a photo-emission analyzing method.
The photo-emission analyzing method is a method of determining the position of failure on the IC chip in the case where the IC failure mode is a DC characteristic failure such as latch-up and junction collapse. In the case of a MOS type IC, little current flows through a PN junction of a normal transistor, but, in the case of the failure mode, a large quantity of junction current flows, and an excess of the current generates far infrared rays, which are detected by a special detector to thereby determine the position of failure. Although far infrared rays are radiated also in the case of heat generation due to short-circuit of metallic components at wiring portions, the wavelength band in such failure is different from that in the case of the above-mentioned failure mode, so that observation of the far infrared rays is carried out by switching over the wavelength sensitivity.
As has been described above, in the photo-emission analyzing method, it is necessary to detect the far infrared rays coming from a PN junction portion of the transistor. Where the number of aluminum wiring layers provided on the upper side of the PN junction portion is larger, the wirings intersect complicatedly with each other in a network form, so that the far infrared rays radiated from the lowest layer are blocked by the wirings when observed from the face side of the IC chip. Therefore, where the IC chip is formed in a multi-layer wiring structure, observation from the face side of the IC chip is impossible.
However, the far infrared rays can pass through bulk silicon, so that observation of far infrared rays is carried out from the back side of the IC chip opposite to the wiring layer side.
At the time of analyzing a defective IC, power source is applied so as to obtain a normal IC chip operation mode, and analysis is conducted by holding the IC chip in a timing suitable for easy determination.
Therefore, in the case of the IC 20, cutting the metallic substrate 22 has some influence on heat radiation properties but has no influence on the operation of the IC chip 21, so that radiation of far infrared rays can be observed by mechanically cutting the metallic substrate 22 at the portion where the IC chip 21 is present.
In the case of a normal quad flat package (QFP) type IC, the IC chip is constituted by face-up bonding, and, therefore, the mold is cut from the back side, and finally a lead frame is cut to expose the back side of the IC chip (effective signal wires are ordinarily absent in the lead frame).
However, in the case of the IC 30, although it is possible to cut the sealing resin 34 on the upper side of the IC chip 31 and expose the IC chip 31, a power source wiring portion must be removed with a special chemical because a power source layer is provided on the surface of the IC chip 31. The removal may increase the impedance of the power source wiring portion, and may remove necessary portions, resulting in some case in that the IC chip 31 does not operate actually. In addition, as has been describe above, the observation of the far infrared rays from the side of the sealing resin 34 is hampered by the layers of aluminum wirings on the upper side of PN junctions of the IC chip 31. Namely, the aluminum wirings appear as complicated intersections in a network form as viewed from the side of the sealing resin 34, so that far infrared rays are shut off, and analysis by photo-emission is impossible.
On the other hand, at the time of observing the far infrared rays from the back side (lower side) of the sealing resin 34, the whole surface of the IC chip 31 is covered by the package substrate 32, so that a central portion of the package substrate 32 where the IC chip is present must be cut away. The package substrate 32 naturally contains innumerable wiring patterns, so that it is impossible to easily remove the central portion of the package substrate 32 by cutting. It may be contemplated to design wiring so that wiring patterns are absent at a portion on the lower side of the IC chip 31, but it is wasteful that this portion cannot be utilized for pattern wiring. In the case where wiring is so designed that the wiring patterns can be utilized effectively as much as possible, it is necessary to remove the package substrate 32 to accurately expose the whole surface of the IC chip 31 while minimizing the area of removal of the package substrate 32, but it is ordinarily difficult to externally recognize the position of the IC chip mounted inside.
The present invention has been made to solve the above-mentioned problems. Accordingly, it is an object of the invention to provide a semiconductor device and a method of inspecting the same in which photo-emission analysis can be carried out without processing an upper layer wiring portion or the like of an IC chip.
In order to attain the above object, according to one aspect of the present invention, there is provided a semiconductor device comprising a package substrate provided on its face side with a plurality of wiring patterns such as electrode lands and wirings and provided on its back side with a plurality of electrode bumps corresponding to the wiring patterns, a semiconductor chip provided with an electronic circuit integrated, the semiconductor chip mounted and fixed on the face side of the package substrate in a face-up manner, and a sealing member sealing the semiconductor chip, wherein an indication indicating the position of the semiconductor chip is provided on the back side of the package substrate.
Further, according to another aspect of the present invention, an indication in the semiconductor device may be a mark for providing an opening by removing the back side of the package substrate in the case of analyzing a failure reason of the semiconductor device by a photo-emission analyzing method.
According to still another aspect of the present invention, the indication in the semiconductor device may be formed by etching in an etching step for forming the wiring patterns of the package substrate.
Furthermore, according to yet another aspect of the present invention, there is provided a method of inspecting a semiconductor device comprising a package substrate provided on its face side with a plurality of wiring patterns such as electrode lands and wirings and provided on its back side with a plurality of electrode bumps corresponding to the wiring patterns, a semiconductor chip provided with an electronic circuit integrated, the semiconductor chip mounted and fixed on the face side of the package substrate in a face-up manner, a sealing member sealing the semiconductor chip, and an indication provided on the back side of the package substrate for indicating the position of the semiconductor chip, the method comprises the steps of removing the package substrate at the portion of an area surrounded by the indication to open and expose the back side of the semiconductor chip, mounting the semiconductor device with the back side of the semiconductor chip exposed on an inspecting circuit substrate, passing an electric current to the semiconductor chip, allowing far infrared rays emitted from a defective portion of the semiconductor chip upon the passage of the electric current to be discharged from the opening, detecting the discharged far infrared rays by a far infrared ray detector, and analyzing the defective portion by a photo-emission analyzing method.
Therefore, according to the present invention, it is possible to easily recognize the region where the semiconductor chip is present of the package substrate to be removed, without additional cost, to form an opening portion by removing a portion of the package substrate without damaging the function of the semiconductor chip, and to easily inspect and analyze the failure portion by the photo-emission analyzing method.
The above and other objects, features and advantages of the present invention will become apparent from the following description and appended claims, taken in conjunction with the accompanying drawings which show by way of example some preferred embodiments of the invention.